Alpha code sequences: (again OpenSource)

If you find them useful, please let me know.

• Byte swapping sequences
• Multimedia sequences
• 32-bit Rotate sequences

• Byte swapping: 8 bytes at a time (By Dick Sites)
  This one is useful to swap large regions of memory (arrays), and was originally written with the 21064 in mind.
  Input: 0x1122334455667788 (in memory)
  
  

Instruction	Value
LDG f1, &mem	f1: 0x7788556633441122
STT f1, &tmp_area
LDQ r1, &tmp_area	f1: 0x7788556633441122
ZAP r1, #0xaa, r2	r2: 0x0088006600440022
ZAP r1, #0x55, r3	r3: 0x7700550033001100
SLL r2, 0x8, r2	r2: 0x8800660044002200
SRL r3, 0x8, r3	r3: 0x0077005500330011
OR r2, r3, r0	r0: 0x8877665544332211

By using the FTOIT instruction in the 21264, the sequence can be:

Instruction	Value
LDG f1, &mem	f1: 0x7788556633441122
FTOIT f1, r1	f1: 0x7788556633441122
ZAP r1, #0xaa, r2	r2: 0x0088006600440022
ZAP r1, #0x55, r3	r3: 0x7700550033001100
SLL r2, 0x8, r2	r2: 0x8800660044002200
SRL r3, 0x8, r3	r3: 0x0077005500330011
OR r2, r3, r0	r0: 0x8877665544332211





• Byte swapping: signed 32-bit item (by Richard Gorton & Anton Chernoff)
  Input: 0xAABBCCDD (in a register)
  
  

Instruction	Value
EXTWL src, 1, tmp1	tmp1: 0x0000BBCC
EXTBL src, 3, tmp2	tmp2: 0x000000AA
INSBL src, 3, tmp3	tmp3: 0xDD000000
ANDNOT tmp1, 0xff, tgt	tgt: 0x0000BB00
INSBL tmp1, 2, tmp1	tmp1: 0x00CC0000
ADDL tmp2, tmp3, tmp2	tmp2: 0xDD0000AA
ADDL tmp1, tmp2, tmp1	tmp1: 0xDDCC00AA
ADDL tgt, tmp1, tgt	tmp1: 0xDDCCBBAA

For an unsigned 32-bit version, simply replace the last ADDL with an OR



• Byte swapping: signed 32-bit item (by Mike Burrows)
  Input: 0xXXXXXXXXAABBCCDD (X meaning irrelevant)
  
  

Instruction	Value
INSLH a0, 7, v0	v0: 0000000000AABBCC
INSWL a0, 3, a0	a0: 000000CCDD000000
BIS a0, v0, a0	v0: 000000CCDDAABBCC
SRL a0, 16, v0	v0: 0000000000CCDDAA
ZAPNOT a0, 0xa, a0	a0: 00000000DD00BB00
ZAP v0, 0xa, v0	v0: 0000000000CC00AA
ADDL v0, a0, v0	v0: 00000000DDCCBBAA

For an unsigned 32-bit version, simply replace the last ADDL with an OR



• Byte swapping: signed 32-bit item assuming 21164PC or 21264 (by Mike Burrows)
  Input: 0xXXXXXXXXAABBCCDD (X meaning irrelevant)
  
  

Instruction	Value
UNPKBW a0, v0	v0: 00AA00BB00CC00DD
SLL v0, 24, a0	a0: BB00CC00DD000000
BIS v0, a0, a0	a0: BBAACCBBDDCC00DD
EXTWL a0, 6, v0	v0: 000000000000BBAA
ZAP a0, 0xf3, a0	a0: 00000000DDCC0000
ADDL a0, v0, v0	v0: 00000000DDCCBBAA

For an unsigned 32-bit version, simply replace the last ADDL with an OR



• Byte swapping using memory: unsigned 32-bit item assuming 21264 (by Mike Burrows)
  Input: 0xXXXXXXXXAABBCCDD (X meaning irrelevant)
  
  

Instruction	Value
UNPKBW a0, v0	v0: 00AA00BB00CC00DD
STQ v0, 0(sp)
LDG f0, 0(sp)	f0: 00DD00CC00BB00AA
FTOIT f0, v0	v0: 00DD00CC00BB00AA
PKWB v0, v0	a0: 00000000DDCCBBAA

For a signed 32-bit version, add 'ADDL v0, 0, v0' to the sequence

• Multimedia sequences
  Convervsion of 0x8844773366225511 into 0x8877665544332211
  A basic ev56 version. 15 instructions long

Instruction	Value
ZAP a0, 0x55, t1	t1: 0x8800770066005500
SLL t1, 0x8, t2	t2: 0x0077006600550000
OR t1, t2, t3	t3: 0x8877776666555500
ZAP t3, 0x33, t4	t4: 0x8877000066550000
SLL t4, 0x10, t5	t5: 0x0000665500000000
OR t4, t5, t6	t6: 0x8877665566550000
ZAP t6, 0xf, t7	t7: 0x8877665500000000
ZAP a0, 0xAA, t8	t8: 0x0044003300220011
SRL t8, 0x8, t9	t9: 0x0000440033002200
OR t8, t9, t10	t2: 0x0044443333222211
ZAP t10, 0xCC, t11	t11: 0x0000443300002211
SRL t11, 0x10, t12	t12: 0x0000000044330000
OR t11, t12, a1	a1: 0x0000443344332211
ZAP a1, 0xf0, a2	a2: 0x0000000044332211
OR t7, a2, v0	r0: 0x8877665544332211

• Multimedia: Convervsion of 0x8844773366225511 into 0x8877665544332211
  An improved ev56 version. 14 instructions long

Instruction	Value
ZAP a0, 0x55, t1	t1: 0x8800770066005500
SLL t1, 0x8, t2	t2: 0x0077006600550000
OR t1, t2, t3	t3: 0x8877776666555500
ZAP t3, 0x03, t4	t4: 0x0000000066550000
ZAP t3, 0x3f, t5	t5: 0x8877000000000000
ZAP a0, 0xAA, t8	t8: 0x0044003300220011
SLL t8, 0x8, t9	t9: 0x4400330022001100
OR t8, t9, t10	t10: 0x4444333322221111
EXTWL t10, 0x5, t11	t11: 0x0000000000004433
OR t4, t11, t12	t12: 0x0000000066554433
SLL t12, 0x10, t6	t6: 0x0000665544330000
EXTWL t10, 0x1, t7	t7: 0x0000000000002211
OR t5, t7, a1	a1: 0x8877000000002211
OR t6, a1, v0	v0: 0x8877665544332211

• Multimedia: Convervsion of 0x8844773366225511 into 0x8877665544332211
  The 'obvious' use of PK instructions.

Instruction	Value
PKWB a0, t1	t1: 0x0000000044332211
SRL a0, 0x8, t2	t2: 0x0088447733662255
PKWB t2, t3	t3: 0x88776655
SLL t3, 0x20, v0	v0: 0x8877665500000000
OR v0, t1, v0	v0: 0x8877665544332211

Unfortunately, the PK* instructions take 3 cycles on ev6, and requires the U0 pipeline. A maximal throughput version for ev6 would probably use a copy of the ev6 code interleaved with a second copy of ev56 code, producing 2 results more or less simultaneously.

• 32-bit Rotate sequences (the 64-bit ones are obvious)
  The paired (dual) sequences are useful if there are a large number of items to rotate. There is some setup code required to generate masks, but that code can be put outside of a loop. The dual rotate right equivalents are easily derived from the rotate left ones.
  • Rotate 32-bit item left N bits
  • Rotate 32-bit item right N bits
  • Paired (dual) 32-bit rotate left 1 bit
  • Paired (dual) 32-bit rotate left N bits
• Rotate 32-bit item left N bits:
  0x00000000f0006000 --> 0x00000000c0018003 (for N=2)
  

  Instruction	Value
  SLL a0, N, t1	t1: 0x00000003c0018000
  EXTLL t1, 4, t2	t1: 0x0000000000000003
  OR t1, t2, t3	t1: 0x00000003c0018003
  ZAP t3, 0xf0, v0	t1: 0x00000000c0018003

  
  
• Rotate 32-bit item right N bits:
  0x00000000f0006008 --> 0x000000003c001802 (for N=2)
  

  Instruction	Value
  SLL a0, 32, t1	t1: 0xf000600800000000
  OR a0, t1, t2	t1: 0xf0006008f0060008
  SRL t2, N, t3	t1: 0x3c0018023c001802
  ZAP t3, 0xf0, v0	t1: 0x000000003c001802

  
  
• Paired (dual) Rotate 32-bit item left 1 bit:
  0xf000000ff0006000 --> 0xe000001fe000c001
  

  Instruction	Value
  LDAH t5, 0x4000(r31)	t1: 0x0000000040000000
  S4ADDQ t5, 1, mask	t1: 0x0000000100000001
  SRL a0, 31, t1	t1: 0x00000001e000000f
  ADDQ a0, a0, t2	t1: 0xe000001fe000c000
  AND t1, mask, t3	t1: 0x0000000100000001
  BIC t2, mask, t4	t1: 0xe000001ee000c000
  OR t3, t4, v0	t1: 0xe000001fe000c001

  
  
• Paired (dual) Rotate 32-bit item left N bits:
  0x70000001e0006000 --> 0xc000000780018003 (for N == 2)
  

  Instruction	Value
  LDA mask, 1(r31)	t1: 0x0000000000000001
  SLL mask, N, mask	t1: 0x0000000000000004
  SUBQ mask, 1, mask	t1: 0x0000000000000003
  SLL mask, 32, t1	t1: 0x0000000300000000
  OR mask, t1, mask	t1: 0x0000000300000003
  LDA t2, 31(r31)	t1: 0x000000000000001f
  SUBQ t2, N, count	t1: 0x000000000000001f
  SRL a0, count, t1	t1: 0x00000001e000000f
  SLL a0, N, t2	t1: 0xe000001fe000c000
  AND t1, mask, t3	t1: 0x0000000100000001
  BIC t2, mask, t4	t1: 0xe000001ee000c000
  OR t3, t4, v0	t1: 0xe000001fe000c001